1. Field of the Invention
The present invention relates to a phase shift mask used in a photolithography process for forming a miniaturized pattern on a semiconductor device etc. and to a method of exposure and a method of producing a semiconductor device using the same, in particular a phase shift mask, a method of exposure, and a method of producing a semiconductor device able to make a line width of a miniaturized pattern uniform.
2. Description of the Related Art
Along with improvements in the performance of semiconductor devices, greater miniaturization and higher density packaging have become demanded in the semiconductor production process. Therefore, when forming resist patterns by photolithography, it is also required to form miniaturized patterns exceeding the resolution limit determined by the wavelength of the light and optical system.
In recent years, as a method for forming a miniaturized pattern of less than the exposure wavelength, a multiple exposure method using a Levenson phase shift mask has been employed. This method of exposure comprises exposure using a Levenson phase shift mask and exposure using a mask other than a Levenson phase shift mask.
As a mask other than a Levenson phase shift mask, usually a binary mask comprised of a light-blocking film formed with apertures passing light is used. However, it is also possible to perform the multiple exposure by combining a half-tone type phase shift mask using a material having a certain transmittance as a light-blocking film etc. together with a Levenson phase shift mask.
When performing exposure using a Levenson phase shift mask, miniaturized patterns exceeding the resolution limit determined by the wavelength of the light and optical system can be transferred, but unnecessary patterns are generated between regions opposite in phase because of the decrease in light intensity. To eliminate the unnecessary patterns and form patterns not requiring as high a resolution as with a Levenson phase shift mask, at least two exposures are performed.
The multiple exposure method using a Levenson phase shift mask has already been applied commercially for forming gate layers of a high-speed LSI or ULSI etc. A gate layer of a ULSI requires a high controllability of line width in the patterns forming the gate electrodes, so a phase shift mask comprised of an array of phase shifters is used at the pattern forming parts.
FIG. 1A shows an example of the gate layer of a ULSI. As shown in FIG. 1A, an active region 101 of a PMOS and an active region 102 of an NMOS are formed in a substrate. A gate layer 103 is formed on the substrate. The gate layer 103 is comprised of for example polysilicon. The miniaturized pattern parts on the active regions 101 and 102 are the gate electrodes 103a and 103b. A channel is formed below them.
The gate layer 103 at the portions other than the active regions 101 and 102 is formed with a gate contact. For decreasing the resistivity of interconnections, facilitating fabrication of the pattern, etc., the gate layer 103 is made a relatively thick line width at portions other than the gate electrodes 103a and 103b. The portions other than the active regions 101 and 102 and gate layer 103 are element isolation regions.
FIG. 1B shows mask patterns when forming resist patterns for forming the gate layer 103 of FIG. 1A by the multiple exposure method. Here, an example of multiple exposure using a Levenson phase shift mask and binary mask is shown. The resist is assumed to be a positive type resist.
The solid lines in FIG. 1B show the patterns of the Levenson phase shift mask. The hatched portion shows a light-blocking part 104 of the Levenson phase shift mask. Light passes through the phase shifters 105a, 105b, 106a, and 106b other than the light-blocking part 104. The phase shifters 105a and 105b differ from each other in thickness (or optical path length). Due to this, the phase of the light passing through the phase shifters 105a and 105b is inverted. Between the phase shifters 105a and 105b, the light intensity becomes smaller and the resist remains in a narrow line width.
In the same manner, the phase shifters 106a and 106b differ from each other in optical path lengths. Due to this, between the phase shifters 106a and 106b, the resist remains in a narrow line width.
On the other hand, the dotted lines of FIG. 1B show the pattern of the binary mask. This corresponds to the pattern of the gate layer 103 of FIG. 1A in the portion other than the gate electrodes 103a and 103b of FIG. 1A.
The exposure using the Levenson phase shift mask of FIG. 1B and exposure using the binary mask can be performed in any sequence. After the multiple exposure, the resist is developed to form the resist patterns. Using the resist patterns as a mask, the for example polysilicon layer is dry etched to obtain the gate layer 103 shown in FIG. 1A.
However, when using the conventional Levenson phase shift mask described above for exposing the resist, it is not possible to make the line width of the resist constant at the miniaturized patterns of the gate electrodes. A resist for forming the circled part in the gate layer 103 shown in FIG. 2A is shown enlarged in FIG. 2B.
As shown in FIG. 2B, the line width of the resist 107 becomes narrower in the longitudinal direction of the gate electrode (gate width direction) from the center part toward one end. On the other hand, at the end of the gate electrode in the gate width direction, the line width of the resist 107 sharply increases. When forming the gate electrode 103a (see FIG. 2A) by using such a resist 107 as a mask, the gate electrode 103a becomes locally narrow near that one end.
In the same way, the resist line width fluctuates at the other end of the gate electrode 103a or both ends of the gate electrode 103b of FIG. 2A. Therefore, a gate electrode 103a with a uniformly narrow line width cannot be obtained on the active region 101 such as shown in FIG. 2A. The gate electrode 103b on the active region 102 also does not have a uniform line width.
For example, in the case of a CMOS circuit shown in FIG. 2A, due to the local thinning in the line widths of the gate electrodes 103a and 103b, leakage etc. is easily induced and the circuit no longer functions as a CMOS circuit.
Japanese Patent No. 2892014 (Japanese Unexamined Patent Publication (Kokai) No. 2-39152) discloses a method of exposure able to improve the uniformity of line width when forming adjacent slit-type patterns by photolithography. According to this method of exposure, as shown in FIG. 3, a mask 114 comprising rectangular patterns 112 and 113 on a support 111 is used for exposure. At the corners of the mask patterns 112 and 113, jog parts 114 and 115 are provided.
If the jog parts 114 and 115 were not formed at the mask patterns 112 and 113, the distribution of light intensity in the part enclosed by the dotted line of FIG. 3 would become as shown in FIG. 4A. As shown in FIG. 4A by the arrow, the light intensity would locally increase near the corners of the patterns and the line width of the resist would fluctuate at these parts.
On the other hand, as shown in FIG. 3, due to the provision of the jog parts 114 and 115 on the mask patterns 112, 113, it becomes possible to make the distance between the transferred patterns constant as shown in FIG. 4B.
However, since the above mask is a binary mask, it cannot be applied to form a miniaturized pattern exceeding the resolution limit determined by the wavelength of the light and the optical system. Also, in the case of the above method of exposure, along with the distance between the patterns becoming constant, rounded shapes at the ends of the patterns become more prominent. Therefore, when miniaturizing patterns, this is sometimes conversely disadvantageous in forming patterns with a high precision.